Power dissipation is becoming a limiting factor in the realisation of VLSI systems. The paper describes two different techniques which employ Genetic Algorithms (GA) for synthesis of digital circuits. The first employs a multi-objective genetic algorithm for structurally synthesising low power circuits. A gate-level description of the circuit is encoded into a single chromosome and the GA evolves by searching for circuit structures that are optimised for both overall capacitive area and critical path. This allows operation under reduced power supply voltages. Although, the technique currently operates at gate-level its main advantages become apparent when used within a high-level framework. Our results are illustrated with examples at the gate-level by using the adder and parity checker problems. The second technique operates on a Data Flow Graph (DFG) consisting of high level blocks such as registers, adders, and multipliers. Operations such as retiming and automatic pipelining are used to reduce the critical path of the DFG, hence allowing operation under reduced supply voltage. Our results are illustrated using an 8th order Avenhaus filter with achievement of more than 50% power saving.