### Automatic transformations from floating-point to fixed-point for implementing digital signal processing algorithms

Abstract

Many digital signal processing and communication algorithms are first simulated
using floating-point arithmetic and later transformed into fixed-point arithmetic
to reduce implementation complexity. This transformation process may take more
than 50% of the design time for complex designs. In addition, wordlengths in
fixed-point designs may be altered at later stages in the design cycle. Different
choices of wordlenghths lead to different tradeoffs between signal and implementation
complexity.
In this dissertation, I propose two methods for characterizing the tradeoffs between
signal quality and implementation complexity during the transformation of digital
system designs to fixed-point arithmetic and variables. The first method, a
gradient-based search for single-objective optimization with sensitivity information,
scales linearly with the number of variables, but can become trapped in local
optima. Based on wordlength design case studies for a wireless communication
demodulator, adding sensitivity information reduces the search time by a factor of
four and yields a design with 30% lower implementation costs.
The second method, a genetic algorithm for multi-objective optimization, provides
a Pareto optimal front that evolves towards the optimal tradeoff curve for signal
quality vs. implementation complexity. This second method can be used to fully
characterize the design space.
I propose to use wordlength reduction methods of signed right shift and truncation
to reduce power consumption in a given hardware architecture. For each method, I
derive the expected values of the number of gates that switch during multiplication
of the inputs. I apply the signed right shift method and the truncation method to
a 16-bit radix-4 modified Booth multiplier and a 16-bit Wallace multiplier. The
truncation method with 8-bit operands reduces the power consumption by 56% in the
Wallace multiplier and 31% in the Booth multiplier. The signed right shift method
shows a 25% power reduction in the Booth multiplier, but no power reduction in the
Wallace multiplier.
Finally, this dissertation describes a method to automate design assistance for
transformation from floating-point to fixed-point data types. Floating point
programs are converted to fixed-point programs by a code generator. Then, the proposed
wordlength search algorithms offer designers the freedom to determine data wordlengths
to optimize the tradeoffs between signal quality and implementation complexity.