The design of modern Very Large Scale Integration (VLSI) devices from a higher abstraction level (algorithmic level) yields much greater productivity compared to designing at lower abstraction levels. However, designing from higher abstraction level (achieved through a process called high-level synthesis) signifies lack of lower-level details during parametric evaluation of alternative architectural choices. Therefore, an ideal solution is to perform meet-in-the middle methodology to reinforce the advantages of both top-down (from algorithmic level) and bottom-up design approaches. This chapter presents a formal design flow from algorithmic level to register transfer level using evolutionary approach as an exploration framework for hardware accelerators. The design process presented using evolutionary techniques is capable of directly converting an application (specified through a control data flow graph) from algorithmic level to its circuit structure at register transfer level.