Network-on-chip (NoC) is considered the next generation of communication infrastructure, which will be omnipresent in different environments. In the platform-based design methodology, an application is implemented by a set of collaborating intellectual property (IP) blocks. The selection of the most suited set of IPs as well as their physical mapping onto the NoC to efficiently implement the application at hand are two hard combinatorial problems. In this article, we propose an innovative power-aware multi-objective evolutionary algorithm to perform the assignment and mapping stages of a platform-based NoC design synthesis tool. Our algorithm uses the well-known multi-objective evolutionary algorithms NSGA-II and microGA as kernels. The optimisation is driven by the required area and the imposed execution time, considering that the decision maker's restriction is the power consumption of the implementation.