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-- Company: 
-- Engineer: 
-- 
-- Create Date: 09/28/2021 11:32:44 AM
-- Design Name: 
-- Module Name: TB_SRL16 - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity TB_SRL16 is
--  Port ( );
end TB_SRL16;

architecture Behavioral of TB_SRL16 is

-- Components Declarations:
--
component SRLC16E
-- pragma translate_off
-- generic (
---- Shift Register initialization ("0" by default) for functional
--simulation:
-- INIT : bit_vector := X"0000"
--);
-- pragma translate_on
 port (
 D : in std_logic;
 CE : in std_logic;
 CLK : in std_logic;
 A0 : in std_logic;
 A1 : in std_logic;
 A2 : in std_logic;
 A3 : in std_logic;
 Q : out std_logic;
 Q15 : out std_logic
);
end component;

--señales de entrada
signal D : std_logic:='0'; 
signal CE : std_logic:='0'; 
signal A : std_logic_vector (3 downto 0):="0000"; 

--señales de salida

signal Q : std_logic;
signal Q15 : std_logic;

--recursos de reloj

constant clk_period : time := 10 ns;
signal clk : std_logic:='0';  


begin

UUT: SRLC16E
 port map (
D => D, -- insert input signal
CE => CE, -- insert Clock Enable signal (optional)
CLK => clk, -- insert Clock signal
A0 => A(0), -- insert Address 0 signal
A1 => A(1), -- insert Address 1 signal
A2 => A(2), -- insert Address 2 signal
A3 => A(3), -- insert Address 3 signal
Q => Q, -- insert output signal
Q15 => Q15 -- insert cascadable output signal
);


-- Clock process definitions
clk_process :process
begin
	clk <= '1';
	wait for clk_period/2;
    clk <= '0';
	wait for clk_period/2;
end process;
   
--proceso de generacion de señales
prueba:process
begin
    CE <= '1';
    A <= "0101";
    wait for clk_period;
    D <= '1';
    wait for clk_period;
    D <= '0';
    wait for clk_period;   
    D <= '0';
    wait for clk_period;
    D <= '1';
    wait for clk_period; 
    D <= '0';
    wait for clk_period*3; 
    A <= "1101";
      
wait;
end process;

end Behavioral;