----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 09/09/2021 10:36:59 AM
-- Design Name: 
-- Module Name: ACC - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ACC is
    Generic (N:Integer:=32);
    Port ( A : in STD_LOGIC_VECTOR (N-1 downto 0);
           ce : in STD_LOGIC;
           rst : in STD_LOGIC;
           clk : in STD_LOGIC;
           S : out STD_LOGIC_VECTOR (N-1 downto 0));
end ACC;

architecture Behavioral of ACC is

component Reg_N is
    Generic (N:Integer:=8);
    Port ( A : in STD_LOGIC_VECTOR (N-1 downto 0);
           ce : in STD_LOGIC;
           clk : in STD_LOGIC;
           S : out STD_LOGIC_VECTOR (N-1 downto 0));
end component;

Signal inReg,outReg : std_logic_vector (N-1 downto 0);
Signal inADD1,inADD2,outADD : std_logic_vector (N-1 downto 0);
Signal zero : std_logic_vector (N-1 downto 0):=(others=>'0');

begin

acumulador : Reg_N generic map (N=>N) port map (A=>inReg,ce=>ce,clk=>clk,S=>outReg);

sumador : entity work.adder_nbits generic map (N=>N) port map (A=>inADD1,B=>inADD2,S=>outADD);

muxACC : entity work.mux2x1 generic map (N=>N) port map (A=>outADD,B=>zero,sel=>rst,S=>inReg);

RegIn : Reg_N generic map (N=>N) port map (A=>A,ce=>ce,clk=>clk,S=>inADD2);

inADD1 <= outReg;

S <= outReg;

end Behavioral;