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-- Company: 
-- Engineer: 
-- 
-- Create Date: 09/21/2021 10:22:37 AM
-- Design Name: 
-- Module Name: TB_ctrl_unit - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TB_ctrl_unit is
--  Port ( );
end TB_ctrl_unit;

architecture Behavioral of TB_ctrl_unit is

-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk : std_logic; 

--Señales de la entidad a prueba
--entradas
signal start : std_logic:='0';
signal err : std_logic:='0';
signal complete : std_logic:='0';
signal finish : std_logic:='0';
signal rst : std_logic:='0';

--salidas
signal sel_mux1,sel_mux2 : std_logic;
signal sel_op : std_logic_vector (1 downto 0);

begin

UUT : entity work.control_Unit port map ( start=>start,
           err => err,
           complete => complete,
           finish => finish,
           clk => clk,
           rst => rst,
           sel_mux1=>sel_mux1,
           sel_mux2=>sel_mux2,
           sel_op=>sel_op
           
           );
           

-- Clock process definitions
clk_process :process
begin
    clk <= '1';
	wait for clk_period/2;
	clk <= '0';
	wait for clk_period/2;
end process;

-- Señales de prueba
signals : process
begin
    wait for 100 ns;
    rst <= '1';
    wait for clk_period;
    rst <= '0';
    wait for 10*clk_period;
    start <= '1';
    wait for clk_period;
    start <= '0';
    wait for 10*clk_period;
    complete <= '1';
    wait for clk_period;
    complete <= '0';
    
    wait for 5*clk_period;
    finish <= '1';
    wait for clk_period;
    finish <= '0';    
    wait for 5*clk_period;
    complete <= '1';
    wait for clk_period;
    complete <= '0';
--    rst <= '1';
--    wait for clk_period;
--    rst <= '0';
    wait;
end process;

           


end Behavioral;