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-- Company: 
-- Engineer: 
-- 
-- Create Date: 09/14/2021 11:46:27 AM
-- Design Name: 
-- Module Name: control_Unit - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity control_Unit is
    Port ( start : in STD_LOGIC;
           err : in STD_LOGIC;
           complete : in STD_LOGIC;
           finish : in STD_LOGIC;
           clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           sel_mux1 : out STD_LOGIC;
           sel_mux2 : out STD_LOGIC;
           sel_op   : out STD_LOGIC_VECTOR (1 downto 0)
           );
end control_Unit;

architecture Behavioral of control_Unit is

type STATE_TYPE is (
reset_st,
wait_st,
load_st,
filtro_st,
output_st,
end_st
);

signal A_state, N_state: STATE_TYPE:=end_st; 

signal sel_mux1_s,sel_mux2_s : std_logic;
signal sel_mux1_r,sel_mux2_r : std_logic;

signal sel_op_s,sel_op_r : std_logic_vector (1 downto 0);

begin

--reset and registers
process (clk,rst)
begin
	if (clk='1' and clk'event) then  
		if (rst ='1') then  
			A_state <=reset_st;
		else
			A_state <= N_state;
		end if;
	--salidas sincronizadas
	sel_mux1_r <= sel_mux1_s;
	sel_mux2_r <= sel_mux2_s;
	sel_op_r <= sel_op_s;	
    end if;
end process;

--salidas
    sel_op <= sel_op_r;
  	sel_mux1 <= sel_mux1_r;
	sel_mux2 <= sel_mux2_r;
   

transiciones : process(A_state,start,err,complete,finish)
begin
    --valores por default
    N_state <= A_state;
    sel_op_s <= sel_op_r;  
   	sel_mux1_s <= sel_mux1_r;
	sel_mux2_s <= sel_mux2_r;
    
    case A_state is 
        when reset_st =>
            N_state <= wait_st;
            sel_op_s <= "00";
            sel_mux1_s <= '0';
            sel_mux2_s <= '0';
        when wait_st =>
            if start='1' then
                N_state <= load_st;
                sel_op_s <= "01";
            end if;
  
        when load_st =>    
            if err = '1' then
                N_state <= end_st;
            elsif complete='1' then
                N_state <= filtro_st;
                sel_mux1_s <= '1';
                sel_mux2_s <= '1';
            end if;
        when filtro_st =>
            if finish='1' then
                N_state <= output_st;
                sel_op_s <= "00";
            end if;
            
        when output_st =>
            if complete='1' then
                N_state <= end_st;
            end if;
     
        when end_st =>
            N_state <= wait_st;
     end case;

end process; 

end Behavioral;