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-- Company: 
-- Engineer: 
-- 
-- Create Date: 09/21/2021 11:40:23 AM
-- Design Name: 
-- Module Name: RAM_mem - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity RAM_mem is
    Generic (data_size:Integer:=8;
             mem_size:Integer:=8);
    Port ( address : in STD_LOGIC_VECTOR (mem_size-1 downto 0);
           din : in STD_LOGIC_VECTOR (data_size-1 downto 0);
           we : in STD_LOGIC;
           clk : in STD_LOGIC;
           dout : out STD_LOGIC_VECTOR (data_size-1 downto 0));
end RAM_mem;

architecture Behavioral of RAM_mem is

type RAM is array (0 to 2**mem_size-1) of STD_LOGIC_VECTOR (7 downto 0);
signal sbox_lt : RAM ;

begin

process(clk,we)
begin
	if rising_edge(clk) then
		if we='1' then
			sbox_lt(CONV_INTEGER(address)) <= din;
		end if;
		dout <= sbox_lt(CONV_INTEGER(address));

	end if;
end process;

end Behavioral;