----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 09/21/2021 11:46:28 AM
-- Design Name: 
-- Module Name: TB_RAM_mem - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TB_RAM_mem is
    Generic (data_size:Integer:=8;
             mem_size:Integer:=4);
--  Port ( );
end TB_RAM_mem;

architecture Behavioral of TB_RAM_mem is

signal din : std_logic_vector (data_size-1 downto 0):=(others=>'0');
signal address : std_logic_vector (mem_size-1 downto 0):=(others=>'0');

signal we : std_logic:='0';
 
signal dout : std_logic_vector (data_size-1 downto 0):=(others=>'0');

 
 -- Clock period definitions
constant clk_period : time := 10 ns;
constant delay : time := 3 ns;
signal clk : std_logic; 

begin

UUT : entity work.RAM_mem 
    Generic map (data_size=>data_size,
             mem_size=>mem_size)
    Port map ( address => address,
           din => din,
           we => we,
           clk => clk,
           dout => dout );

-- Clock process definitions
clk_process :process
begin
    clk <= '1';
	wait for clk_period/2;
	clk <= '0';
	wait for clk_period/2;
end process;


estimulos:process
begin
    wait for 100 ns;
    we <= '1';
    din <= (others=>'1');
    wait;
end process;


end Behavioral;
----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 09/21/2021 11:46:28 AM
-- Design Name: 
-- Module Name: TB_RAM_mem - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TB_RAM_mem is
    Generic (data_size:Integer:=8;
             mem_size:Integer:=8);
--  Port ( );
end TB_RAM_mem;

architecture Behavioral of TB_RAM_mem is

signal din : std_logic_vector (data_size-1 downto 0):=(others=>'0');
signal address : std_logic_vector (mem_size-1 downto 0):=(others=>'0');

signal we : std_logic:='0';
 
signal dout : std_logic_vector (data_size-1 downto 0):=(others=>'0');

 
 -- Clock period definitions
constant clk_period : time := 10 ns;
constant delay : time := 3 ns;
signal clk : std_logic; 

begin

UUT : entity work.RAM_mem 
    Generic map (data_size=>data_size,
             mem_size=>mem_size)
    Port map ( address => address,
           din => din,
           we => we,
           clk => clk,
           dout => dout );

-- Clock process definitions
clk_process :process
begin
    clk <= '1';
	wait for clk_period/2;
	clk <= '0';
	wait for clk_period/2;
end process;


estimulos:process
begin
    wait for 100 ns;
    we <= '1';
    wait for clk_period*2;
    for i in 0 to 2**mem_size-1 loop    
        din <= std_logic_vector(to_unsigned(i,mem_size));
        address <= std_logic_vector(to_unsigned(i,mem_size));
        wait for clk_period;
    end loop;
    we <= '0';
    wait for clk_period*10;

    for i in 0 to 2**mem_size-1 loop    
        address <= std_logic_vector(to_unsigned(i,mem_size));
        wait for clk_period;
    end loop;

    wait;
end process;


end Behavioral;