----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 09/23/2021 11:09:36 AM
-- Design Name: 
-- Module Name: TB_ipcore - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TB_ipcore is
--  Port ( );
end TB_ipcore;

architecture Behavioral of TB_ipcore is

signal ena : std_logic :='0';
signal enb : std_logic :='0';
signal wea : std_logic_vector (0 downto 0):="0";
signal web : std_logic_vector (0 downto 0):="0";

signal addra : std_logic_vector (7 downto 0):=(others=>'0');
signal addrb : std_logic_vector (7 downto 0):=(others=>'0');

signal dina : std_logic_vector (127 downto 0):=(others=>'0');
signal douta : std_logic_vector (127 downto 0):=(others=>'0');

signal dinb : std_logic_vector (127 downto 0):=(others=>'0');
signal doutb : std_logic_vector (127 downto 0):=(others=>'0');


 -- Clock period definitions
constant clk_period : time := 10 ns;
constant delay : time := 3 ns;
signal clk : std_logic; 


COMPONENT blk_mem_gen_0
  PORT (
    clka : IN STD_LOGIC;
    ena : IN STD_LOGIC;
    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    dina : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
    douta : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
    clkb : IN STD_LOGIC;
    enb : IN STD_LOGIC;
    web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    dinb : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
    doutb : OUT STD_LOGIC_VECTOR(127 DOWNTO 0)
  );
END COMPONENT;



begin

UUT : blk_mem_gen_0
  port map (
    clka =>  clk,
    ena => ena,
    wea => wea,
    addra => addra,
    dina => dina,
    douta => douta,
    clkb => clk,
    enb => enb,
    web => web,
    addrb => addrb,
    dinb => dinb,
    doutb => doutb
  );
  
  
  -- Clock process definitions
clk_process :process
begin
    clk <= '1';
	wait for clk_period/2;
	clk <= '0';
	wait for clk_period/2;
end process;


estimulos:process
begin
    ena <='1';
    enb <='1';
    
    wait for 105 ns;
    wea <="1";
    web <="1";
        
    wait for clk_period;
    for i in 0 to 127 loop    
        addra <= std_logic_vector(to_unsigned(2*i,8));
        addrb <= std_logic_vector(to_unsigned(2*i+1,8));
        
        dina <= std_logic_vector(to_unsigned(2*i,8)) & 
                std_logic_vector(to_unsigned(2*i,8)) &   
                std_logic_vector(to_unsigned(2*i,8)) &   
                std_logic_vector(to_unsigned(2*i,8)) &   
                std_logic_vector(to_unsigned(2*i,8)) &   
                std_logic_vector(to_unsigned(2*i,8)) &   
                std_logic_vector(to_unsigned(2*i,8)) &   
                std_logic_vector(to_unsigned(2*i,8)) &   
                std_logic_vector(to_unsigned(2*i,8)) &   
                std_logic_vector(to_unsigned(2*i,8)) &   
                std_logic_vector(to_unsigned(2*i,8)) &   
                std_logic_vector(to_unsigned(2*i,8)) &   
                std_logic_vector(to_unsigned(2*i,8)) &   
                std_logic_vector(to_unsigned(2*i,8)) &   
                std_logic_vector(to_unsigned(2*i,8)) &
                std_logic_vector(to_unsigned(2*i,8));

        dinb <= std_logic_vector(to_unsigned(2*i+1,8)) & 
                std_logic_vector(to_unsigned(2*i+1,8)) &   
                std_logic_vector(to_unsigned(2*i+1,8)) &   
                std_logic_vector(to_unsigned(2*i+1,8)) &   
                std_logic_vector(to_unsigned(2*i+1,8)) &   
                std_logic_vector(to_unsigned(2*i+1,8)) &   
                std_logic_vector(to_unsigned(2*i+1,8)) &   
                std_logic_vector(to_unsigned(2*i+1,8)) &   
                std_logic_vector(to_unsigned(2*i+1,8)) &   
                std_logic_vector(to_unsigned(2*i+1,8)) &   
                std_logic_vector(to_unsigned(2*i+1,8)) &   
                std_logic_vector(to_unsigned(2*i+1,8)) &   
                std_logic_vector(to_unsigned(2*i+1,8)) &   
                std_logic_vector(to_unsigned(2*i+1,8)) &   
                std_logic_vector(to_unsigned(2*i+1,8)) &
                std_logic_vector(to_unsigned(2*i+1,8));                  
       
        wait for clk_period;
    end loop;
    wea <="0";
    web <="0";
    wait for clk_period*10;
    
    for i in 0 to 127 loop    
        addra <= std_logic_vector(to_unsigned(2*i,8));
        addrb <= std_logic_vector(to_unsigned(2*i+1,8)); 
    end loop;
    
    wait;
end process;


end Behavioral;