----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 09/13/2021 05:52:06 PM
-- Design Name: 
-- Module Name: multiplier_fp - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity multiplier_fp is
    Generic (int:Integer:=4; dec:Integer:=28);
    Port ( A : in STD_LOGIC_VECTOR (int+dec downto 0);
           B : in STD_LOGIC_VECTOR (int+dec downto 0);
           S : out STD_LOGIC_VECTOR (int+dec downto 0));
end multiplier_fp;

architecture Behavioral of multiplier_fp is

Signal mul : STD_LOGIC_VECTOR ((int+dec)*2 downto 0);

begin

mul <= std_logic_vector(signed(A)*signed(B));

S <= mul(int + 2*dec-1 downto dec-1);

end Behavioral;