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-- Company: 
-- Engineer: 
-- 
-- Create Date: 09/06/2021 09:48:08 PM
-- Design Name: 
-- Module Name: TB_mux4 - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TB_mux4 is
generic (N:Integer:=32);
--  Port ( );
end TB_mux4;

architecture Behavioral of TB_mux4 is

signal A,B,C,D,S : std_logic_vector (N-1 downto 0):=(others=>'0');
signal sel : std_logic_vector (1 downto 0);


begin

UUT : entity work.mux4x1 generic map (N=>N) port map (A=>A,B=>b,C=>C,D=>D,sel=>sel,S=>S);

process
begin
for i in 0 to N/4-1 loop 
    A(4*i+3 downto 4*i) <= X"A";
    B(4*i+3 downto 4*i) <= X"B";
    C(4*i+3 downto 4*i) <= X"C";
    D(4*i+3 downto 4*i) <= X"D";
    
    sel<="11";
    wait for 10 ns;
    sel<="10";
    wait for 10 ns;
    sel<="01";
    wait for 10 ns;
    sel<="00";
    wait for 10 ns;

end loop;
end process;

end Behavioral;