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-- Company: 
-- Engineer: 
-- 
-- Create Date: 09/02/2021 11:11:14 AM
-- Design Name: 
-- Module Name: mux4x1 - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux4x1 is
    Generic (N:Integer:=32);
    Port ( A : in STD_LOGIC_VECTOR (N-1 downto 0);
           B : in STD_LOGIC_VECTOR (N-1 downto 0);
           C : in STD_LOGIC_VECTOR (N-1 downto 0);
           D : in STD_LOGIC_VECTOR (N-1 downto 0);
           sel : in STD_LOGIC_VECTOR (1 downto 0);
           S : out STD_LOGIC_VECTOR (N-1 downto 0));
end mux4x1;

architecture Behavioral of mux4x1 is

begin

--    with sel select
--		S <= A when "00",
--	         B when "01",
--	         C when "10",
--	         D when others;

muxes: for i in 0 to N-1 generate
    mux_i: entity work.mux4x1_bit port map (A=>A(i),B=>B(i),C=>C(i),D=>D(i),sel=>sel,S=>S(i));
end generate;


end Behavioral;