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-- Company: 
-- Engineer: 
-- 
-- Create Date: 09/02/2021 11:34:34 AM
-- Design Name: 
-- Module Name: mux4x1_bit - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux4x1_bit is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           C : in STD_LOGIC;
           D : in STD_LOGIC;
           sel : in STD_LOGIC_VECTOR (1 downto 0);
           S : out STD_LOGIC);
end mux4x1_bit;

architecture Behavioral of mux4x1_bit is

begin

    with sel select
    	S <= A when "00",
             B when "01",
 	         C when "10",
	         D when others;

end Behavioral;