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-- Company: 
-- Engineer: 
-- 
-- Create Date: 09/07/2021 11:49:51 AM
-- Design Name: 
-- Module Name: Reg_N - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Reg_N is
    Generic (N:Integer:=8);
    Port ( A : in STD_LOGIC_VECTOR (N-1 downto 0);
           ce : in STD_LOGIC;
           clk : in STD_LOGIC;
           S : out STD_LOGIC_VECTOR (N-1 downto 0));
end Reg_N;

architecture Behavioral of Reg_N is

begin

reg_process : process(clk)
begin
    if rising_edge(clk) and ce='1' then
        S <= A;
    end if;
end process;


end Behavioral;