----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 09/07/2021 10:57:17 AM
-- Design Name: 
-- Module Name: TB_adder - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TB_adder is
--  Port ( );
end TB_adder;

architecture Behavioral of TB_adder is

signal A,B,Cin,S,Cout : std_logic:='0';

begin

UUT : entity work.adder port map (A=>A,B=>B,Cin=>Cin,S=>S,Cout=>Cout);

process
begin
    A <= '0';B<='0';Cin<='0';
    wait for 10 ns;
    A <= '0';B<='0';Cin<='1';
    wait for 10 ns;
    A <= '0';B<='1';Cin<='0';
    wait for 10 ns;
    A <= '0';B<='1';Cin<='1';
    wait for 10 ns;
    A <= '1';B<='0';Cin<='0';
    wait for 10 ns;
    A <= '1';B<='0';Cin<='1';
    wait for 10 ns;
    A <= '1';B<='1';Cin<='0';
    wait for 10 ns;
    A <= '1';B<='1';Cin<='1';
    wait for 10 ns;
end process;

end Behavioral;