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-- Company: 
-- Engineer: 
-- 
-- Create Date: 09/07/2021 11:07:47 AM
-- Design Name: 
-- Module Name: TB_adders_chain - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TB_adders_chain is
generic(N:Integer:=8);
--  Port ( );
end TB_adders_chain;

architecture Behavioral of TB_adders_chain is

signal A,B,S,Cout : std_logic_vector (N-1 downto 0):=(others=>'0');
signal Cin : std_logic_vector (N downto 0):=(others=>'0');
begin

Cin(0) <='0';

adders : for i in 0 to N-1 generate
    UUT : entity work.adder port map (B=>B(i),Cin=>Cin(i),S=>S(i),Cout=>Cout(i),A=>A(i));
    Cin(i+1) <= Cout(i);
end generate;

process
begin
    A <= (others=>'0');B<=(others=>'0');
    wait for 10 ns;
    A <= (others=>'0');B<=(others=>'0');
    wait for 10 ns;
    A <= (others=>'0');B<=(others=>'1');
    wait for 10 ns;
    A <= (others=>'0');B<=(others=>'1');
    wait for 10 ns;
    A <= (others=>'1');B<=(others=>'0');
    wait for 10 ns;
    A <= (others=>'1');B<=(others=>'0');
    wait for 10 ns;
    A <= (others=>'1');B<=(others=>'1');
    wait for 10 ns;
    A <= (others=>'1');B<=(others=>'1');
    wait for 10 ns;
    
    A <= X"0F";B <= X"0F";
    wait for 10 ns;

    A <= X"FF";B <= X"FF";
    wait for 10 ns;
    
    
end process;

end Behavioral;