----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 09/07/2021 11:35:50 AM
-- Design Name: 
-- Module Name: adder_nbits - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity adder_nbits is
    Generic (N:Integer:=8);
    Port ( A : in STD_LOGIC_VECTOR (N-1 downto 0);
           B : in STD_LOGIC_VECTOR (N-1 downto 0);
           S : out STD_LOGIC_VECTOR (N downto 0));
end adder_nbits;

architecture Behavioral of adder_nbits is

signal Cin : std_logic_vector (N downto 0):=(others=>'0');
signal Cout : std_logic_vector (N-1 downto 0):=(others=>'0');

begin

adders : for i in 0 to N-1 generate
    UUT : entity work.adder port map (B=>B(i),Cin=>Cin(i),S=>S(i),Cout=>Cout(i),A=>A(i));
    Cin(i+1) <= Cout(i);
end generate;

S(N) <= Cin(N);


end Behavioral;