23.02.2026

A basic element on our FPGA are “lookup tables” with 4 inputs and a single output
resulting from any function of the inputs. Hence, a 4-input multiplexer is the
preferred element. In order to be able to shift by any amount between 0 and 31,
three stages are required. The first shifts by 0, 1, 2, or 3 bits,
the second by 0, 4, 8, or 12 bits, and the third by 0 or 16 bits.
The following signals are involved:

wire [31:0] t1, t2, t3;  // Registros de 32 bits
wire [1:0] sc1, sc0;     // shift counts, 2 bits, puede contar 00, 01, 10, 11

Shifts by 0 to 31 bits.

Etapa 1, 0 1 2 3
Etapa 2, 0 4 8 12
Etapa 3, 0 16

31 = 16 + 12 + 3 = 31 
     28

The shifter input is a (un registro) B,
its output is t3.

 The intermediate outputs between multiplexers are t1 and t2.
The shift count is split into

assign sc0 = C1[1:0];   // Los 2 bits menos significativos, codifica 0,1,2,3
assign sc1 = C1[3:2];   // Los siguiente 2 bits menos significativos 4,5,6,7

// Corrimiento a la izquierda

assign t1 = (sc0 == 3) ? {B[28:0], 3'b0} : // shifter for LSL
            (sc0 == 2) ? {B[29:0], 2'b0} :
            (sc0 == 1) ? {B[30:0], 1'b0} : B;

assign t2 = (sc1 == 3) ? {t1[19:0], 12'b0} :
            (sc1 == 2) ? {t1[23:0], 8'b0} :
            (sc1 == 1) ? {t1[27:0], 4'b0} : t1;

assign t3 = C1[4] ? {t2[15:0], 16'b0} : t2;
          si n=16              16 ceros
                   16 bits de t2

Ok!!!

// Corrimiento a la derecha
// Sirve tanto para el corrimiento como para el
// corrimiento circular

wire [31:0] s1, s2, s3;

assign s1 = (sc0 == 3) ? {(w ? B[2:0] : {3{B[31]}}), B[31:3]} : // shifter for ASR and ROR
            (sc0 == 2) ? {(w ? B[1:0] : {2{B[31]}}), B[31:2]} :
            (sc0 == 1) ? {(w ? B[0] : B[31]), B[31:1]} : B;

assign s2 = (sc1 == 3) ? {(w ? s1[11:0] : {12{s1[31]}}), s1[31:12]} :
            (sc1 == 2) ? {(w ? s1[7:0] : {8{s1[31]}}), s1[31:8]} :
            (sc1 == 1) ? {(w ? s1[3:0] : {4{s1[31]}}), s1[31:4]} : s1;

assign s3 = C1[4] ? {(w ? s2[15:0] : {16{s2[31]}}), s2[31:16]} : s2;


w es el bit que IR[16] que indica que es un corrimiento circular

w = IR[16];

La instrucción 2 es el corrimiento a la derecha, 
la instrucción 3 es el corrimiento circular a la derecha

op = IR[19:16];

Ok!!!

